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triple differential receiver with 300m adjustable line equalization preliminary technical data AD8122 rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features compensates cables to 30 0 meters for wideband video 60 mhz equalized bw @ 300 meters of utp cable 120 mhz equalized bw @ 150 meters of utp cable fast time domain performance 70 ns settling time to 1% with 300 meters of utp cable 7 ns rise/fall tim es with 2 v step @ 30 0 meters of utp cable three frequency response gain adjustment pins high frequency peaking adjustment (v peak ) output lowpass filter cutoff adjustment (v filte r ) broadband flat gain adjustment (v gain ) selectable for utp or coax compensat ion dc output offset adjust (v offset ) low output offset voltage: 4 mv @ g = 1 compensates both rgb and ypbpr two on - chip comparators with hysteresis can be used for common - mode sync extraction available in 40- lead , 6 mm 6 mm lfcsp applications keyboar d - video - mouse (kvm) digital signage rgb video over utp cable s professional video projection and distribution hd v ideo security video functional block dia gram out r + in r ? in r ad 8122 out g + in g ? in g out b + in b ? in b ? in cmp 1 + in cmp 1 ? in cmp 2 + in cmp 2 out cmp 2 out cmp 1 v peak v offset v gain gain r gain g gain b v filter coax/utp figure 1. general description the a d812 2 is a triple , hi gh speed, differential receiver and equalizer that compensates for the transmission losses of utp and coaxial cables up to 300 meters in length . various gain stages are summed together to best approximate the inverse freque ncy response of the cable. each channel features a high impedance differential input that is ideal for interfacing directly with the cable. the AD8122 has two control inputs for optimal cable compensation, one lpf control input, an input to select between utp and coax cable, and an output offset adjust input. the cable compensation inputs are used to compensate for different cable lengths; the v peak input controls the amount of high frequency peaking and the v gain input adjusts the broadband flat gain, which co mpens ates for the flat cable loss. the v filter input controls the cutoff frequency of output lowpass filters on each channel. selection between utp and coaxial cable compensation responses is determined by the binary coax/ utp for added flexibility, the gains of each channel can be set to x1 or x2 using the associated gain cont rol pins . input, which can be left floating in utp applications. the v offset pin allows the dc voltage at the output to be adjusted, which can be useful in dc - coupled systems. the ad812 2 is available in a 6 mm 6 mm , 40- lead lfcsp and is rated to operate over the extended temperature range of ? 40 c to +85 c.
AD8122 preliminary technical data rev. prc | page 2 of 13 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 function al block diagram .............................................................. 1 general description ......................................................................... 1 revision history .......................... error! bookmark not defined. spec ifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function description .............................. 7 theory of operation ........................................................................ 9 input single - ended voltage range considerations ................. 9 applications information .............................................................. 10 basic operation .......................................................................... 10 input overdrive recovery and protection .............................. 10 comparators ............................................................................... 10 sync pulse extraction u sing comparators ............................. 11 using the v peak , v gain , v filter , and v offset inputs ................. 11 using the coax/ utp driving high - z and capacitive loads .................................... 12 selector ................................................... 12 driving 75 ? cable with the AD8122 .................................... 12 layout and power supply decoupling considerations ......... 12 input common - mode range ................................................... 12 power - down ............................................................................... 12 outline dimensions ....................................................................... 13
preliminary technical data AD8122 rev. prc | page 3 of 13 specifications t a = 25c, v s = 5 v, r l = 150 ?, g = 2, belden cable (bl - 7987r), v offset = 0 v, v peak and v gain are set to optimum settings, unless otherwise noted . table 1 . parameter conditions min typ m ax unit dynamic and noise performance C 3 db large signal bandwidth v out = 2 v p - p, AD8122 alone 1 5 5 mhz v out = 2 v p - p, 150 meters cat -5 110 mhz v out = 2 v p - p, 300 meters cat -5 57 mhz v out = 1 v p - p, AD8122 alone, r l = 1 k ? , g = 1 260 mhz v out = 1 v p - p, 150 meters cat -5 , r l = 1 k ? , g = 1 120 mhz v out = 1 v p - p, 300 meters cat -5 , r l = 1 k ? , g = 1 60 mhz slew rate v out = 2 v p - p, AD8122 alone v/sec 10% to 90% rise/fall time v out = 2 v step, 150 meters cat -5 6 ns v out = 2 v step, 30 0 meters cat -5 7 ns v out = 1 v step, 150 meters cat -5 , r l = 1 k ? , g = 1 6 ns v out = 1 v step, 30 0 meters cat -5 , r l = 1 k ? , g = 1 7 ns settling time to 1 % v out = 2 v step, 150 meters cat -5 ns v out = 2 v step, 300 meters cat -5 7 0 ns v out = 1 v step, 150 meters cat -5 , r l = 1 k ? , g = 1 ns v out = 1 v step, 300 meters cat -5 , r l = 1 k ? , g = 1 70 ns integrated output voltage noise 150 meter setting, integrated to 160 mhz 2.5 mv rms 300 meter setting, integrated to 160 m hz 1 6 mv rms input performance input voltage range single - ended, ?in and +in 4 .0 v maximum differential voltage swing 3 v p -p voltage gain error g = 1, v o / v i , v gain set for 0 meters of cable 2 % g = 2, v o / v i , v gain set for 0 meters of cable 2 % channel - to - channel gain matching g = 1, v peak , v gain set for 300 meters of cable 0. 2 % g = 2, v peak , v gain set for 300 meters of cable 0. 2 % common - mode rejection (cmr ) at dc, v peak = v gain = 0 v , g = 1/g = 2 ? 92/ ? 85 db at dc, v peak , v gain set for 300 meters of cable db at 1 mhz, v peak , v gain set for 300 meters of cable g = 1/g = 2 ? 66/ ? 60 db at 50 mhz, v peak , v gain set for 300 meters of cable g = 1/g = 2 +4/+10 db at 1 00 mhz, v peak , v gain set for 300 met ers of cable g = 1/g = 2 +8/+11 db input resistance common mode 4.4 m ? differential 3.7 m ? input capacitance common mode 1.0 pf differential 0.5 pf input bias current 1.1 a v offset pin current 2.0 a v gain pin current 1.0 a v peak pin current 1.0 a v filter pin current 1.0 a coax/ utp logic 0/logic1 pin current ? 1/ 24 a adjustment pins v peak input voltage range relative to gnd 0 to 2 v v gain input voltage range relative to gnd 0 to 2 v v offset to out gain r ange limited by output swing , g = 1, v gain = 0v 1 v/v
AD8122 preliminary technical data rev. prc | page 4 of 13 parameter conditions min typ m ax unit output characteristics output voltage swing ?3. 9 to +3. 9 v r l = 1 k ? , g = 1 v output offset voltage rto , v peak = v gain = v filter = v offset = 0 v , g = 1 , r l = 1 k ? 4 mv rto , control inputs set for 300 meters of cable mv output offset voltage drift r to v/c power supply operating voltage range 4.5 5.5 v positive quiescent supply current 1 20 ma negative quiescent supply curre nt 6 6 ma supply current drift, i cc /i ee a/c positive power supply rejection ratio dc, referred to output ? 7 0 db 100 mhz, referred to output db negative power supply rejection ratio dc, referred to output ? 81 db 100 mhz, referred to o utput db power down, v ih (minimum) minimum logic 1 voltage 1.1 v power down, v il (maximum) maximum logic 0 voltage 0.8 v positive supply current, powered down v peak = v gain = v pole = 0 v 3. 4 m a negative supply current, powered down v peak = v ga in = v pole = 0 v 0. 4 m a comparators output voltage levels v oh /v ol 3.33/0. 3 3 v hysteresis v hyst 73 mv propagation delay t pd, lh /t pd, hl 14/10 ns rise/fall times t rise /t fal l 10/ 7 ns output resistance ? operating temperature range ?40 +85 c
preliminary technical data AD8122 rev. prc | page 5 of 13 figure 2. equalized frequency response for various cable lengths figure 3. settling time, g = 1, r l = 1k ?
AD8122 preliminary technical data rev. prc | page 6 of 13 absolute maximum rat ings table 2 . parameter rating supply voltage 11 v power dissipation see figure 4 input voltage ( any in put) v s ? ? 0.3 v to v s+ + 0.3 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at thes e or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating con ditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, ja is spec i fied for the device soldered in a circuit board in still air. table 3 . thermal resistance with the underside pad connected to the plane package type/pcb type ja u nit 40- lead lfcsp/4 - layer tbd c/w maximum power dissipation the maximum safe power dissipation in the ad812 2 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass tra n sition temp er ature, the plastic changes its properties. even te m porarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad812 2 . exceeding a junction te m perature of 175 c for an extended time can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the pac k age due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipation due to each load current is calculated by multiplying the load current by the voltage difference between the associated power supply and the output voltage. the total power dissipation due to load currents is then obtained by taking the sum of the individual power dissipations. rms output voltages must be used when dealing with ac si g nals. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb su r face that is thermally connected to a so lid plane (usually the ground plane) to achieve the spec i fied ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 40 - lead lfcsp (29c/w) on a jedec standard 4 - la yer board with the underside paddle soldered to a pad that is thermally connected to a pcb plane. ja values are approxim a tions. figure 4 . maximum power dissipation vs. temperature for a 4 - layer board esd caution
preliminary technical data AD8122 rev. prc | page 7 of 13 pin conf iguration and functi on description 1 gain b 1 2 3 4 5 6 7 8 9 10 23 24 25 26 27 28 29 30 22 21 1 1 1 2 1 3 1 5 1 7 1 6 1 8 1 9 2 0 1 4 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 3 2 3 1 top view ( not to scale ) ad 8122 2 nc = no connect notes 1 . exposed paddle on the bottom of the package must be connected to a pcb ground plane to achieve specified thermal resistance. out b v s+ v s? gain g out g v s+ gain r out r dgnd dv s- v offset dv s+ v gain v peak v filter pd coax / utp v s? nc agnd agnd agnd ?in b +in b ?in g +in g ?in r +in r v s+_cmp v s?_cmp nc ?in cmp1 +in cmp1 out cmp1 ?in cmp2 +in cmp2 out cmp2 v s? v s+ figure 5 . pin configuration table 4 . pin function descriptions pin o. nemonic description 1, 40 nc no internal connection . 2 +in cmp1 posi tive input, comparator 1 . 3 ? in cmp1 negative input, comparator 1 . 4 out cmp1 output, comparator 1 . 5 v s+ _ cmp positive power supply, comparator . connect to +5v . 6 v s ? _ cmp negative power supply, comparator. connect to ? 5v . 7 out cmp2 output, comparator 2. 8 ?in cmp2 negative input, c omparator 2. 9 +in cmp2 positive input, comparator 2. 10 , 14, 18 v s ? negative power supply , equalizer sections. connect to ? 5v . 11 gain b blue channel gain. connect to out b for g = 1; connect to gnd for g = 2. 12 out b output, blue channel . 13, 1 7 , 21 v s+ positive power supply, equalizer sections . connect to +5v . 15 gain g green channel gain. connect to out g for g = 1; connect to gnd for g = 2. 1 6 out g output, green channel . 19 gain r red channel gain. connect to out r for g = 1; connect to gnd for g = 2. 20 out r output, red channel. 22 d v s ? negative power supply, digital control . connect to ? 5v . 23 v offset output offset control voltage . 24 d gnd digital ground reference . 25 v gain broadband flat gain control voltage . 26 v peak equalizer high frequency boost control voltage . 27 v filter low pass filter cutoff frequency adjustment control voltage .
AD8122 preliminary technical data rev. prc | page 8 of 13 28 pd power down . 29 d v s + positive power supply, digital control . connect to +5v . 30 coax/ utp cable compensation control input. connect to logic 1 for coax , logic 0 for utp. 31 +in r positive input, red channel. 32 ?in r negative input, red channel. 33, 36, 39 agnd analog ground reference 34 +in g positive input, green channel. 35 ?in g negative input, green channel. 37 +in b positive input, blue channel. 38 ?in b negative input, blue channel. exposed underside pad thermal plane connection. connect to any pcb plane with voltage between v s+ and v s ? .
preliminary technical data AD8122 rev. prc | page 9 of 13 theory of operation the ad812 2 is a triple , wideband, low noise analog line equalizer that compensates for losses in utp and coaxial cables up to 300 meters in length. the 3 - channel a rchitecture is targeted at high resolution rgb applications but can be used in hd ypbpr applications as well . the transfer function of theAD8122 can be pin - selected for utp or coaxial cable, and t he gain of each channel can be set to 1 or 2 . four continuously adjustable control voltages, common to the rgb channels, are available to the designer to provide compensation for various cable lengths as well as for variations in the cable itself. the v peak input is used to control the amount of hi gh frequency peaking. v peak is the control that is used to compensate for frequency and cable - length dependent, high frequency losses that are present due to the skin effect of t he cable. a second control pin, v gain , is used to adjust broadband gain to com pensate for low frequency flat losses present in the cable. a third control pin, v filter , is used to adjust the cutoff frequency of the output lowpass filters. finally, an output offset adjust control, v offset , allows the designer to shift the output dc level. the ad812 2 has a high impedance differential input that makes termination simple and allows dc - coupled signals to be received directly from the cable. the ad812 2 input can also be used in a single - ended fashion in coaxial cable applications. for dif ferential systems that require very wide input common - mode range, the ad8143 high - voltage triple differential receiver c an be placed in front of the ad812 2 . the ad812 2 has a low impedance output that is capable of driving a 150 ? load. for systems where the ad812 2 has to drive a high impedance capacitive load , it is recommended that a small series resistor be placed be tween the output and load t o buffer the capacitance . the resistor should not be so large as to reduce the overall bandwidth to an unacceptable level. two comparators are provided on - chip that can be used for sync pulse extraction in systems that use sync - on - common mode encoding. each comparator has very low output impedance and can therefore be us ed in a source - only cable termina tion scheme by placing a series resistor equal to the cable characteristic impedance directly on the comparator output. additional details are provided in the applications information section. inpu t single - ended voltage range considerations when using the ad812 2 as a receiver, it is important to ensure that its single - ended input voltage s stay within the ir specified range s. t he received single - ended level for each input is calculated by adding the c ommon - mode level of the driver, the single - ended peak amplitude of the received signal, the amplitude of any sync pulses, and the other induced common - mode signals , such as ground shifts bet ween the driver and the ad812 2 and pickup from external sources , s uch as power lines and fluorescent lights. see the applications information section for more details.
AD8122 preliminary technical data rev. prc | page 10 of 13 application s information basic operation the ad812 2 is easy to apply because it contains everything on - chip needed for cable loss compensation . figure 8 shows a basic application circuit (power supplies not shown) with common - mode sync pulse extraction that is compatible with the common - mode sync pulse encoding technique used in the ad8134 , ad8142, ad8147 , and ad8148 triple differential drivers. if sync extraction is not required, the terminations can be single 100 ? resistors , and the comparator inputs can be left floating . input overdrive recovery and protect ion occasion al large differential transients can occur on the cable due to a number of causes, such as esd and switching. when operating the AD8122 at g = 1, a differential input that exceeds +3.4v or - 3.4v will cause the output to stick at the associated power supply rail (positive rail for positive overdrive, negative rail for negative overdrive) . the AD8122 recovers from this condition when the magni tude of the differential input falls below 200 mv. m ost video signals return to nominally zero volts during the blanking intervals, therefore recovery from the overdriven condition in systems that use these signals would occur during the first blanking in terval tha t occurs after the overdrive event has passed. in systems with g = 1 that employ video signals that do not return to zero, such as those that include dc offsets, it is necessary to prevent the overdrive condition from occurring. in these cases t he protection circuit illustrated in figure 6 , which limits the differential input voltage to a little over 2v, should be placed between the termination resistors and each AD8122 differential input . the overdrive condition does not occur in applications with g = 2. 49.9 1 6 2 5 3 4 hn2d02futw1t1 1 6 2 5 3 4 49.9 hn2d02futw1t1 termination resistors AD8122 input figure 6. required input protection for applications with g = 1 comparators while t he two on - chip comparators are most often used to extract video sync pulses fro m the received common - mode voltages as shown in figure 8 , they may also be used to recover sync pulses in sync - on - color applications, to receive differential digital information received on other channels such as the fourth utp pa ir , or as general purpose comparators . built - in hysteresis helps to eliminate false triggers from noise. the sync pulse extraction using comparators section describes the sync extraction details. the comparator outpu ts have nea rly 0 ? output impedance and are designed to dri ve source - terminated transmission lines. the source termination technique uses a resistor in series with each comparator output such that the sum of the comparator source resistance ( 0 ?) and the series resistor e quals the transmission line characteristic impedance. the load end of the transmission line is high impedance. when the signal is launched into the source termination, its initial value is one - half of its source value because its amplitude is divided by tw o in the voltage divider formed by the source termination and the transmission line. at the load, the signal experiences nearly 100% positive reflection due to the high impedance load and is restored to nearly its full value. this technique is commonly use d in pcb layouts that involve high speed digital logic. figure 7 shows how to apply the comparators with source termination when driving a 50 ? transmission line that is high impedance at its receive end. 06814-021 49 .9 ? high-z z 0 = 50 ? figure 7 . using comparator with source termination
preliminary technical data AD8122 rev. prc | page 11 of 13 16 red blue green cmv red cmv blue cmv AD8122 16 12 7 4 peak 25 26 27 28 v v filter v gain hsync out vsync out 32 31 green 35 34 38 37 3 2 8 9 received red video received green video received blue video red video out green video out blue video out analog control inputs power down control pd 1 2 1k ? 1k ? 49.9 ? 49.9 ? 49.9 ? 475 ? 49.9 ? 49.9 ? 49.9 ? 47 pf 47 pf 19 red gain 15 green gain 11 blue gain 23 v offset 30 cable select control coax/utp figure 8 . basic application circuit with common - mode sync extraction (supplies and input protection not shown) sync pulse extractio n using compa rators the ad812 2 is useful in many systems that transport computer vid eo signals, which are typically comprise d of red, green, and blue video signals and separate horizontal and vertical sync signals (rgb hv) . because the sync signals are separate and not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common - mode voltages of the rgb signals. t he ad8134 , ad8142, ad8147 , and ad8148 triple differential driver s are natural complement s to the ad812 2 because they perform the sync pulse encoding with the necessary circuitry on - chip. th e sync encoding equations follow: [ ] h v k v red cm ? = 2 ( 1 ) [ ] v 2 2 ? = k v green cm ( 2 ) [ ] h v k v blue cm + = 2 ( 3 ) where: red v cm , green v cm , and blue v cm are the transmitted common - mode voltages of the respective color signals. k is an adjustable gain constant that is set by the driver . v and h are the vertical and horizontal sync pulses, defined with a weight of ?1 when the pulses are in their low states, and a weight of +1 when they are in their high states. the ad8134 , ad8142 and ad8146/ad8147/ad8148 data sheet s con tain further details regarding the encoding scheme. figure 8 i llustrates how the ad812 2 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the rgb common - mode voltages by th e aforementioned drivers . using the v peak , v gain , v filter , and v offset inputs the v peak input is the main peaking control and is used to compensate for the low - pass roll - off in the cable response. the v gain input controls the wideband flat gain and is used t o compensate for the cable loss that is nominally flat. the output of each channel contains an on - chip adjustable lowpass filter to reduce high frequency noise. in most applications, the filter cutoff frequency control, v filter , is connected directly to the v peak voltage in order to provide maximum bandwidth and minimum noise for a given v peak setting. external lowpass filters are generally not required. the v offset input is used to produce an offset at the ad812 2 output. the output offset is equal to th e voltage applied to the v offset input, limited by the output swing limits.
AD8122 preliminary technical data rev. prc | page 12 of 13 using the coax/ utp connect this input to logic 1 (or +5v) for coaxial cable and logic 0 (or gnd) for utp cable. this input has an internal pulldown res istor, and can therefore be left floating in utp applications. selector driving high - z and capacitive load s in many rgb - over - utp applications, delay correction is required to remove the skew that exists among the three pairs used to carry the rgb signals. the ad8 120 is ideally suited to perform this skew correction, and can be placed immediately following the AD8122 in the receiver signal chain. the ad8120 has a high input impedance, and a fixed gain of two. when using the ad8120 with the AD8122 , the AD8122 shou ld be configured for a gain of one by connecting each video output to its respective gain pin. when driving a high impedance capacitive input, it is necessary to place a small series resistor between each of the three ad812 2 video outputs and the load to buffer the input capacitance of the device being driven. clearly, the resistor value must be small enough to preserve the required bandwidth. d riving 75 ? cable with the ad812 2 when the rgb outputs must drive a 75 ? line rather than a high impedance load, an additional gain of two is required to make up for the double termination loss (75 ? source and load terminations) . each output of the AD8122 is easily configured for a gain of two by grounding the respective gain pin. layout and power sup ply decou p li ng considerations standard high speed pcb layout practices should be adhered to when designing with the ad812 2 . a solid ground plane is required and controlled impedance traces should be used when interconnecting t he high speed signals. source termination resistors on all of the outputs must be placed as close as possible to the output pins. t he exposed paddle on the underside of the ad812 2 must be connected to a pad that connects to at least one pcb plane. several thermal vias should be used to make the c onnection between the pad and the plane(s). high quality 0.1 f power supply decoupling capacitors should be placed as close as possible to all of the supply pins. small surface - mount ceramic capacitors should be used for these, and tantalum capacitors are recommended for bulk supply decoupling. input common - mode range most applications that use the ad812 2 as a receiver use a driver (such as one from the ad8146/ad8147/ad8148 family , the ad8133 , or the ad8134 ) powered from 5 v supplies. this places the common - mode voltage on the line nominally at 0 v relative to the ground potential at the driver and provides optimum immunit y from any common - mode anomalies picked up along the cable (including ground shifts between the driver and receiver ends). in many of these applications, the ad812 2 input voltage range of typically 4 v is sufficient. if wider input range is required, the ad8143 triple receiver (input common - mode range equals 10.5 v on 12 v supplies) may be placed in front of the ad812 2 . figure 9 illustrates how thi s is done for one ch annel. 100 ? 49.9 ? 1 2 3 received signa l +5v one AD8122 input one ad8143 channe l power supplies = 12v ?5v hbat-540c figure 9. optional use of ad8143 in front of ad812 2 for wide input common - mode range the schottky diodes are required to protect the ad812 2 from any ad8143 outputs that may exceed the AD8122 input limits. the 49.9 ? resistor limits the fault current and produces a pole at approximately 800 mhz with the effective diode capacitance of 3 pf and the ad812 2 input capacitance of 1 p f. t h e pole drops the res ponse by only 0.07 db at 100 mhz and therefore has a negligible effect on the signal. when using a single 5 v supply on the driver side, the common - mode voltage at the driver output is typically 2.5v, or fixed at 1.5v in the case of the ad8142 . the largest received differential video signal is approximately 700 mv p - p, and this therefore adds 175 mv peak to each single - ended side of the differential signal , resulting in a worst - case peak voltage of 2.675 v or 1.675 v on an ad812 2 single - ended input (presumin g there is no ground shift between driver and receiver) . these levels are within the ad812 2 input voltage swing limits, and such a system works well as long as the difference in ground potential between driver and receiver does not cause the input voltage swing to exceed these limits. when used, c ommon - mode sync signals are generally applied with a peak deviation of 500 mv during the blanking interval s (video = 0v), and thereby increase the com mon - mode level from 2.5 v to 3 .0 v , or 1.5v to 2.0v in the cas e of the ad8142 . th ese common - mode level s are below the upper input voltage swing limit of 4 v , and therefore le ave 1 v or 2 v margin for ground shifts between driver and receiver . there are t wo ways to increase the common - mode range of the overall system . one is to p ower the driver from dual supplies (output common - mode voltage = 0 v) and the other is to place an ad8143 in fr ont of the ad812 2 , as shown in figure 9 . the se techniques may be combined or applied separately. power - down the power - down feature is intended to be used to reduce power consumption when a particular device is not in use and does not place the output in a high - z state when asserted. the input logic levels and supply current in power - down mode are presented in the power supply section of table 1 .
preliminary technical data AD8122 rev. prc | page 13 of 13 outline dimensions figure 10 . 40 - lead lead frame chip scale package [lfcsp _ w q ] 6 mm 6 mm body , very very thin quad (cp - 40 - 12 ) dimensions shown in millimeters pubcode: pr10780 - 0 - 5/12(prc)

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